VLSI PRACTICAL: FLIP FLOPS
Q.Prgram to implement SR FlipFlop.
module sr_ff(q,qbar,clk,reset,s,r);
output q,qbar;
input clk,reset,s,r;
reg q;
always@(posedge clk)
begin
if(reset)
q<=0;
else if(s==0&&r==0)
q<=q;
else if(s==0&&r==1)
q<=0;
else if(s==1&&r==0)
q<=1;
else if(s==1&&r==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module sr_fftb;
//
Inputs
reg
clk;
reg
reset;
reg s;
reg r;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
sr_ff
uut (
.q(q),
.qbar(qbar),
.clk(clk),
.reset(reset),
.s(s),
.r(r)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
s
= 0;
r
= 0;
#10
reset=0;s=0;r=0;
#10
s=0;r=1;
#10
s=1;r=0;
#10
s=1;r=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
end
endmodule
OUTPUT-
Q. Prgram to implement JK FlipFlop.
module jk_flipflop(q,qbar,reset,clk,j,k);
output q,qbar;
input reset,clk,j,k;
reg q;
wire qbar;
always@(posedge clk)
begin
if(reset)
q<=0;
else if(j==0&&k==0)
q<=q;
else if(j==0&&k==1)
q<=0;
else if(j==1&&k==0)
q<=1;
else if(j==1&&k==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module jk_flipfloptb;
//
Inputs
reg
reset;
reg clk;
reg j;
reg k;
//
Outputs
wire q; wire qbar;
//
Instantiate the Unit Under Test (UUT)
jk_flipflop
uut (
.q(q),
.qbar(qbar),
.reset(reset),
.clk(clk),
.j(j),
.k(k)
);
initial
begin
//
Initialize Inputs
reset
= 1;
clk
= 0;
j
= 0;
k
= 0;
#10
reset=0;j=0;k=0;
#10
j=0;k=1;
#10
j=1;k=0;
#10
j=1;k=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
End
Endmodule
OUTPUT-
Q. Prgram to implement T FlipFlop.
module t_ff(q,clk,reset,t);
output q;
input clk,reset,t;
reg q;
always@(posedge clk)
if(reset)
begin
q<=0;
end
else if(t==0)
begin
q<=q;
end
else if(t==1)
begin
q<=~q;
end
endmodule
TESTBENCH-
module t_fftb;
//
Inputs
reg
clk;
reg
reset;
reg t;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
t_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.t(t)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
t
= 0;
#10 reset=0;t=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
#100;
// Add stimulus
here
end
endmodule
OUTPUT-
Q.Program to implement
D FlipFlop.
module d_ff(q,clk,reset,d);
output q;
input clk,reset,d;
reg q;
always @(posedge clk)
if(reset)
begin
q<=0;
end
else begin
q<=d;
end
endmodule
TESTBENCH-
module d_fftb;
//
Inputs
reg
clk;
reg
reset;
reg d;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
d_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.d(d)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 0;
d=0;
#10 reset=0;d=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
// Add stimulus here
End
Endmodule
OUTPUT-
Q. Program to implement SR Latch.
module sr_latch(q,qbar,clk,reset,s,r);
output q,qbar;
input clk,reset,s,r;
reg q;
always@(clk)
begin
if(reset)
q<=0;
else if(s==0&&r==0)
q<=1;
else if(s==0&&r==1)
q<=0;
else if(s==1&&r==0)
q<=1;
else if(s==1&&r==1)
q<=0;
end
assign qbar=~q;
endmodule
TESTBENCH-
module sr_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg s;
reg r;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
sr_ff
uut (
.q(q),
.qbar(qbar),
.clk(clk),
.reset(reset),
.s(s),
.r(r)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
s
= 0;
r
= 0;
#10
reset=0;s=0;r=0;
#10
s=0;r=1;
#10
s=1;r=0;
#10
s=1;r=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
end
endmodule
OUTPUT-
Q. Program to implement
JK Latch.
module jk_latch(q,qbar,reset,clk,j,k);
output q,qbar;
input reset,clk,j,k;
reg q;
wire qbar;
always@(clk)
begin
if(reset)
q<=0;
else if(j==0&&k==0)
q<=q;
else if(j==0&&k==1)
q<=0;
else if(j==1&&k==0)
q<=1;
else if(j==1&&k==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module jk_latchtb;
//
Inputs
reg
reset;
reg
clk;
reg j;
reg k;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
jk_flipflop
uut (
.q(q),
.qbar(qbar),
.reset(reset),
.clk(clk),
.j(j),
.k(k)
);
initial
begin
//
Initialize Inputs
reset
= 1;
clk
= 0;
j
= 0;
k
= 0;
#10
reset=0;j=0;k=0;
#10
j=0;k=1;
#10
j=1;k=0;
#10
j=1;k=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
endmodule
OUTPUT-
Q.Program to implement T Latch.
module t_latch(q,clk,reset,t);
output q;
input clk,reset,t;
reg q;
always@(clk)
if(reset)
begin
q<=0;
end
else if(t==0)
begin
q<=q;
end
else if(t==1)
begin
q<=~q;
end
endmodule
TESTBENCH-
module t_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg t;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
t_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.t(t)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
t
= 0;
#10 reset=0;t=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
#100;
// Add
stimulus here
end
endmodule
OUTPUT-
Q.Program to implement D Latch.
module d_latch(q,clk,reset,d);
output q;
input clk,reset,d;
reg q;
always @(clk)
if(reset)
begin
q<=0;
end
else begin
q<=d;
end
endmodule
TESTBENCH-
module d_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg d;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
d_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.d(d)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 0;
d=0;
#10 reset=0;d=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
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