VLSI PROJECT
LOVELY PROFESSIONAL UNIVERSITY
LOVELY PROFESSIONAL UNIVERSITY
MINI PROJECT ON 8 BIT CARRY SAVE ADDER
TABLE
OF CONTENTS
I.
NEED OF CSA
II.
INTRODUCTION TO CSA
III.
CSA EQUATION
IV.
8 BIT CSA
V.
MAIN PROGRAM
VI.
OUTPUT
VII.
OUTPUT WAVEFORM
VIII.
APPLICATION
OF CSA
NEED OF CSA
A carry-look-ahead
adder can add two n-bit numbers in O(log n) time. Perhaps
surprisingly, adding three n-bit numbers takes only a constant
additional amount of time. The trick is to reduce the problem of adding three
numbers to the problem of adding just two numbers.
Given three n-bit numbers x =
xn-1, xn-2, . . . . , x0
, y =
yn-1, yn-2, . . . , y0
, and z =
zn-1,zn-2, . . . , z0
, an n-bit carry-save
adder produces an n-bit number u =
un-1, un-2, . . . , u0
and an (n + 1)-bit number v =
vn, vn-1, . . . , v0
such that










u + v = x + y + z.
As shown in Figure, it does this by computing
ui = parity (xi, yi,
zi),
vi + 1 = majority (xi, yi,
zi),
For i = 0, 1, . . . , n - 1. Bit v0 always equals 0.

The n-bit carry-save adder shown in Figure consists
of n full adders FA0, FA1, . . . , FAn - 1. For i = 0, 1, . . . , n - 1, full adder FAi takes inputs xi, yi, and zi.
The sum-bit output of FAi is taken as ui, and the carry-out
of FAi is taken as vi+1. Bit v0 is hardwired to 0.
Since the computations of all 2n + 1 output bits are independent, they can be performed in parallel. Thus,
a carry-save adder operates in
(1) time and has
(n) size. To sum three n-bit numbers, therefore, we need only perform a carry-save addition,
taking
(1) time, and then perform a carry look-ahead
addition, taking O(lg n) time. Although this method is not asymptotically better than the
method of using two carry look-ahead additions, it is much faster in practice.
Moreover, we know that carry-save addition is central to fast algorithms for
multiplication.



INTRODUCTION TO CSA
Carry save adder (CSA) is the design of a high-speed multi operand adder. A carry save adder consists of a ladder of stand-alone full adders. The n-bit CSA consists of n disjoint full adders (FAs) where each of which computes a single sum and carry bit based on the corresponding bits of the three input numbers. It consumes
three n-bit input integers
to be added and produces
two outputs, n-bit partial sum and n-bit carry. Unlike the normal adders such as ripple carry adder, a CSA
consists of multiple one-bit full adders without any carry chaining.
Carry save adder also known as (3, 2) counter where the addends
are three. The carry save adder block diagram can be seen in the figure 2.2. It sums three 4-bits inputs,
and returns the result as two 4-bits output. 3:2 counter can be used to speed up the summation of three or more addends. 3:2 counter can be used to speed up the summation of three or more addends.
If the addends are four or more, more than one
layer of counter is necessary
and there are various possible design for the circuit which the
most common are Dadda and Wallace
trees.
A carry-save adder is described
in Figure:1 An n-bit adder that does not connect up the carries. It is simply a
parallel ensemble of n full-adders without any horizontal connection, and the
carry is saved as an output and not propagated to the next higher-order adder.
The latency of a carry-save adder is the same as that of a full adder. It
reduces the addition of 3 numbers to the addition of 2 numbers, which is known
as the 3:2 compressor since it takes 3 inputs and compresses them down to 2
output numbers. The propagation delay is independent of the number of bits, and
the amount of circuitry is less than a carry select adder. However, CSA has
disadvantages. It does not actually solve the problem of adding two integers
and producing a single output. Instead, it adds three integers and produces two
such that sum of these two is equal to the sum of three inputs. A general equation
of an n-bit CSA is described below accordingly. Three n-bit integers A, B
and C are added to produce two integers Sum and C’ as
CSA
EQUATION
Sum
+ C' = A + B +
C- (11)
And the i th bit of the
sum and the (i+1) th bit of the carry Ci+1’ is calculated
by using the following equations
Sumi
= Ai Å Bi
Å Ci- (12)
Ci
+ 1' = Ai × Bi
+ Ai × Ci
+ Bi × Ci-
(13)
Pipelining of a carry-save adder
is different compared to the previous adder structures. An example of an n-bit
CSA with two pipeline stages is presented in Figure 8 showing that there is no
performance gain from pipelining for a CSA -- the delay of a pipelined CSA is
the same as the non-pipelined CSA. The register is inserted between the carry
of the most significant bit of the lower block, and it is rippled to the upper
block. However, the carry passed through the register is not needed for the
calculation of the sum and carry of the upper block, due to the inherent
characteristics of CSA that the delay is independent of the carries, as
equation (13) presents. In this way, the delay from C1’ to Cn’ is identical to
the delay in each pipelining block, in which the delay equals to that of a
1-bit full adder. The sum is the concatenation of the sum results of the two
blocks.


MAIN PROGRAM-
module
save_carry(f_sum,f_carry,sum,carry,a,b,c,en);
output [7:0]f_sum;
output f_carry;
inout [7:0]sum;
inout [8:1]carry;
wire [7:0]sum;
wire [8:1]carry;
wire [7:0]f_sum;
wire f_carry;
input [7:0]a;
input [7:0]b;
input [7:0]c;
input en;
wire w1,w2,w3,w4,w5,w6;
fa_rajeev
f1(sum[0],carry[1],a[0],b[0],c[0]);
fa_rajeev
f2(sum[1],carry[2],a[1],b[1],c[1]);
fa_rajeev
f3(sum[2],carry[3],a[2],b[2],c[2]);
fa_rajeev
f4(sum[3],carry[4],a[3],b[3],c[3]);
fa_rajeev
f5(sum[4],carry[5],a[4],b[4],c[4]);
fa_rajeev
f6(sum[5],carry[6],a[5],b[5],c[5]);
fa_rajeev f7(sum[6],carry[7],a[6],b[6],c[6]);
fa_rajeev
f8(sum[7],carry[8],a[7],b[7],c[7]);
assign f_sum[0]=sum[0];
ha_df h9(f_sum[1],w1,sum[1],carry[1]);
fa_rajeev
f10(f_sum[2],w2,sum[2],carry[2],w1);
fa_rajeev
f11(f_sum[3],w3,sum[3],carry[3],w2);
fa_rajeev f12(f_sum[4],w4,sum[4],carry[4],w3);
fa_rajeev
f13(f_sum[5],w5,sum[5],carry[5],w4);
fa_rajeev
f14(f_sum[6],w6,sum[6],carry[6],w5);
fa_rajeev
f15(f_sum[7],f_carry,sum[7],carry[7],w6);
endmodule
module fa_rajeev(sum,carry,x,y,z);
input x,y,z;
output sum,carry;
assign sum=(x^y)^z;
assign carry=(x&y)|(z&(x^y));
endmodule
module ha_df(sum,carry,x,y);
input x,y;
output carry,sum;
assign sum=x^y;
assign carry=x&y;
endmodule
TESTBENCH-
module save_carrytb;
//
Inputs
reg
[7:0] a;
reg
[7:0] b;
reg
[7:0] c;
reg
en;
//
Outputs
wire
[7:0] f_sum;
wire
f_carry;
//
Bidirs
wire
[7:0] sum;
wire
[8:1] carry;
//
Instantiate the Unit Under Test (UUT)
save_carry
uut (
.f_sum(f_sum),
.f_carry(f_carry),
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.c(c),
.en(en)
);
initial
begin // Initialize Inputs
forever
#2
en=~en;
initial begin
en=1'b0; c=8'h00;a=8'h00;b=8'h00;
#1
en=1'b1;c=8'h01;a=8'h01;b=8'h01;
#1 c=8'h02;a=8'h02;b=8'h02;
#1 c=8'h03;a=8'h03;b=8'h03;
#1
c=8'h04;a=8'h04;b=8'h04;
#1
c=8'h05;a=8'h05;b=8'h05;
#1 c=8'h06;a=8'h06;b=8'h06;
#1
c=8'h07;a=8'h07;b=8'h07;
#1
c=8'h08;a=8'h08;b=8'h08;
#1
c=8'h09;a=8'h09;b=8'h09;
#1
c=8'h10;a=8'h10;b=8'h10;
#1
c=8'h11;a=8'h11;b=8'h11;
#1
c=8'h12;a=8'h12;b=8'h12;
#1
c=8'h13;a=8'h11;b=8'h13;
#1
c=8'h14;a=8'h14;b=8'h14;
#1
c=8'h15;a=8'h15;b=8'h15;
#1
c=8'h16;a=8'h16;b=8'h16;
#1
c=8'h17;a=8'h17;b=8'h17;
#1
c=8'h18;a=8'h18;b=8'h18;
#1
c=8'h19;a=8'h19;b=8'h19;
#1
c=8'h1a;a=8'h1a;b=8'h1a;
#1
c=8'h1b;a=8'h1b;b=8'h1b;
#1
c=8'h1c;a=8'h1c;b=8'h1c;
#1 c=8'h1d;a=8'h1d;b=8'h1d;
#1
c=8'h1e;a=8'h1e;b=8'h1e;
#1
c=8'h1f;a=8'h1f;b=8'h1f;
#1 c=8'h20;a=8'h20;b=8'h20;
#1
c=8'h21;a=8'h21;b=8'h21;
#1
c=8'h22;a=8'h22;b=8'h22;
#1
c=8'h23;a=8'h23;b=8'h23;
#1
c=8'h24;a=8'h24;b=8'h24;
#1
c=8'h25;a=8'h25;b=8'h25;
#1
c=8'h26;a=8'h26;b=8'h26;
#1
c=8'h27;a=8'h27;b=8'h27;
#1
c=8'h28;a=8'h28;b=8'h28;
#1
c=8'h22;a=8'h22;b=8'h29;
#1
c=8'h2a;a=8'h2a;b=8'h2a;
#1
c=8'h2b;a=8'h2b;b=8'h2b;
#1 c=8'h2c;a=8'h2c;b=8'h2c;
#1
c=8'h2d;a=8'h2d;b=8'h2d;
#1
c=8'h2e;a=8'h2e;b=8'h2e;
#1 c=8'h2f;a=8'h2f;b=8'h2f;
#1
c=8'h30;a=8'h30;b=8'h30;
#1
c=8'h31;a=8'h31;b=8'h31;
#1
c=8'h32;a=8'h32;b=8'h32;
#1
c=8'h33;a=8'h33;b=8'h33;
#1
c=8'h34;a=8'h34;b=8'h34;
#1
c=8'h35;a=8'h35;b=8'h35;
#1
c=8'h36;a=8'h36;b=8'h36;
#1
c=8'h37;a=8'h37;b=8'h37;
#1
c=8'h38;a=8'h38;b=8'h38;
#1
c=8'h39;a=8'h39;b=8'h39;
#1
c=8'h3a;a=8'h3a;b=8'h3a;
#1
c=8'h3b;a=8'h3b;b=8'h3b;
#1
c=8'h3c;a=8'h3c;b=8'h3c;
#1
c=8'h3d;a=8'h3d;b=8'h3d;
#1
c=8'h3e;a=8'h3e;b=8'h3e;
#1
c=8'h3f;a=8'h3f;b=8'h3f;
#1
c=8'h40;a=8'h40;b=8'h40;
#1
c=8'h41;a=8'h41;b=8'h42;
#1
c=8'h43;a=8'h43;b=8'h43;
#1
c=8'h44;a=8'h44;b=8'h44;
#1
c=8'h45;a=8'h45;b=8'h45;
#1
c=8'h46;a=8'h46;b=8'h46;
#1
c=8'h47;a=8'h47;b=8'h47;
#1
c=8'h48;a=8'h48;b=8'h48;
#1
c=8'h49;a=8'h49;b=8'h49;
#1
c=8'h4a;a=8'h4a;b=8'h4a;
#1
c=8'h4b;a=8'h4b;b=8'h4b;
#1
c=8'h4c;a=8'h4c;b=8'h4c;
#1
c=8'h4d;a=8'h4d;b=8'h4d;
#1
c=8'h4e;a=8'h4e;b=8'h4e;
#1
c=8'h4f;a=8'h4f;b=8'h4f;
#1
c=8'h50;a=8'h50;b=8'h50;
#1
c=8'h51;a=8'h51;b=8'h51;
#1
c=8'h52;a=8'h52;b=8'h52;
#1
c=8'h53;a=8'h53;b=8'h53;
#1
c=8'h54;a=8'h54;b=8'h54;
#1
c=8'h55;a=8'h55;b=8'h55;
#1
c=8'h56;a=8'h56;b=8'h56;
#1
c=8'h57;a=8'h57;b=8'h57;
#1
c=8'h58;a=8'h58;b=8'h58;
#1
c=8'h59;a=8'h59;b=8'h59;
#1
c=8'h5a;a=8'h5a;b=8'h5a;
#1
c=8'h5b;a=8'h5b;b=8'h5b;
#1
c=8'h5c;a=8'h5c;b=8'h5c;
#1
c=8'h5d;a=8'h5d;b=8'h5d;
#1
c=8'h5e;a=8'h5e;b=8'h5e;
#1
c=8'h5f;a=8'h5f;b=8'h5f;
#1
c=8'h6f;a=8'h6f;b=8'h6f;
#1
c=8'h7f;a=8'h7f;b=8'h7f;
#1
c=8'h8f;a=8'h8f;b=8'h8f;
#1
c=8'h9f;a=8'h9f;b=8'h9f;
#1
c=8'haf;a=8'haf;b=8'haf;
#1
c=8'hbf;a=8'hbf;b=8'hbf;
#1 c=8'hcf;a=8'hcf;b=8'hcf;
#1 c=8'hdf;a=8'hdf;b=8'hdf;
#1 c=8'hef;a=8'hef;b=8'hef;
#1 c=8'hff;a=8'hff;b=8'hff;
//
Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
initial
$monitor("t=%d,en=%b,a=%0h,b=%0h,c=%0h,sum=%0h,carry=%0h,f_sum=%0h,f_carry=%0h",$time,en,a,b,c,sum,carry,f_sum,f_carry);
initial #99 $stop;
endmodule
OUTPUT-
t= 0,en=0,a=0,b=0,c=0,sum=0,carry=0,f_sum=0,f_carry=0
t= 1,en=1,a=1,b=1,c=1,sum=1,carry=1,f_sum=3,f_carry=0
t= 2,en=0,a=2,b=2,c=2,sum=2,carry=2,f_sum=6,f_carry=0
t= 3,en=1,a=3,b=3,c=3,sum=3,carry=3,f_sum=9,f_carry=0
t= 4,en=0,a=4,b=4,c=4,sum=4,carry=4,f_sum=c,f_carry=0
t= 5,en=1,a=5,b=5,c=5,sum=5,carry=5,f_sum=f,f_carry=0
t= 6,en=0,a=6,b=6,c=6,sum=6,carry=6,f_sum=12,f_carry=0
t= 7,en=1,a=7,b=7,c=7,sum=7,carry=7,f_sum=15,f_carry=0
t= 8,en=0,a=8,b=8,c=8,sum=8,carry=8,f_sum=18,f_carry=0
t= 9,en=1,a=9,b=9,c=9,sum=9,carry=9,f_sum=1b,f_carry=0
t= 10,en=0,a=10,b=10,c=10,sum=10,carry=10,f_sum=30,f_carry=0
t= 11,en=1,a=11,b=11,c=11,sum=11,carry=11,f_sum=33,f_carry=0
t= 12,en=0,a=12,b=12,c=12,sum=12,carry=12,f_sum=36,f_carry=0
t= 13,en=1,a=11,b=13,c=13,sum=11,carry=13,f_sum=37,f_carry=0
t= 14,en=0,a=14,b=14,c=14,sum=14,carry=14,f_sum=3c,f_carry=0
t= 15,en=1,a=15,b=15,c=15,sum=15,carry=15,f_sum=3f,f_carry=0
t= 16,en=0,a=16,b=16,c=16,sum=16,carry=16,f_sum=42,f_carry=0
t= 17,en=1,a=17,b=17,c=17,sum=17,carry=17,f_sum=45,f_carry=0
t= 18,en=0,a=18,b=18,c=18,sum=18,carry=18,f_sum=48,f_carry=0
t= 19,en=1,a=19,b=19,c=19,sum=19,carry=19,f_sum=4b,f_carry=0
t= 20,en=0,a=1a,b=1a,c=1a,sum=1a,carry=1a,f_sum=4e,f_carry=0
t= 21,en=1,a=1b,b=1b,c=1b,sum=1b,carry=1b,f_sum=51,f_carry=0
t= 22,en=0,a=1c,b=1c,c=1c,sum=1c,carry=1c,f_sum=54,f_carry=0
t= 23,en=1,a=1d,b=1d,c=1d,sum=1d,carry=1d,f_sum=57,f_carry=0
t= 24,en=0,a=1e,b=1e,c=1e,sum=1e,carry=1e,f_sum=5a,f_carry=0
t= 25,en=1,a=1f,b=1f,c=1f,sum=1f,carry=1f,f_sum=5d,f_carry=0
t= 26,en=0,a=20,b=20,c=20,sum=20,carry=20,f_sum=60,f_carry=0
t= 27,en=1,a=21,b=21,c=21,sum=21,carry=21,f_sum=63,f_carry=0
t= 28,en=0,a=22,b=22,c=22,sum=22,carry=22,f_sum=66,f_carry=0
t= 29,en=1,a=23,b=23,c=23,sum=23,carry=23,f_sum=69,f_carry=0
t= 30,en=0,a=24,b=24,c=24,sum=24,carry=24,f_sum=6c,f_carry=0
t= 31,en=1,a=25,b=25,c=25,sum=25,carry=25,f_sum=6f,f_carry=0
t= 32,en=0,a=26,b=26,c=26,sum=26,carry=26,f_sum=72,f_carry=0
t= 33,en=1,a=27,b=27,c=27,sum=27,carry=27,f_sum=75,f_carry=0
t= 34,en=0,a=28,b=28,c=28,sum=28,carry=28,f_sum=78,f_carry=0
t= 35,en=1,a=22,b=29,c=22,sum=29,carry=22,f_sum=6d,f_carry=0
t= 36,en=0,a=2a,b=2a,c=2a,sum=2a,carry=2a,f_sum=7e,f_carry=0
t= 37,en=1,a=2b,b=2b,c=2b,sum=2b,carry=2b,f_sum=81,f_carry=0
t= 38,en=0,a=2c,b=2c,c=2c,sum=2c,carry=2c,f_sum=84,f_carry=0
t= 39,en=1,a=2d,b=2d,c=2d,sum=2d,carry=2d,f_sum=87,f_carry=0
t= 40,en=0,a=2e,b=2e,c=2e,sum=2e,carry=2e,f_sum=8a,f_carry=0
t= 41,en=1,a=2f,b=2f,c=2f,sum=2f,carry=2f,f_sum=8d,f_carry=0
t= 42,en=0,a=30,b=30,c=30,sum=30,carry=30,f_sum=90,f_carry=0
t= 43,en=1,a=31,b=31,c=31,sum=31,carry=31,f_sum=93,f_carry=0
t= 44,en=0,a=32,b=32,c=32,sum=32,carry=32,f_sum=96,f_carry=0
t= 45,en=1,a=33,b=33,c=33,sum=33,carry=33,f_sum=99,f_carry=0
t= 46,en=0,a=34,b=34,c=34,sum=34,carry=34,f_sum=9c,f_carry=0
t= 47,en=1,a=35,b=35,c=35,sum=35,carry=35,f_sum=9f,f_carry=0
t= 48,en=0,a=36,b=36,c=36,sum=36,carry=36,f_sum=a2,f_carry=0
t= 49,en=1,a=37,b=37,c=37,sum=37,carry=37,f_sum=a5,f_carry=0
t= 50,en=0,a=38,b=38,c=38,sum=38,carry=38,f_sum=a8,f_carry=0
t= 51,en=1,a=39,b=39,c=39,sum=39,carry=39,f_sum=ab,f_carry=0
t= 52,en=0,a=3a,b=3a,c=3a,sum=3a,carry=3a,f_sum=ae,f_carry=0
t= 53,en=1,a=3b,b=3b,c=3b,sum=3b,carry=3b,f_sum=b1,f_carry=0
t= 54,en=0,a=3c,b=3c,c=3c,sum=3c,carry=3c,f_sum=b4,f_carry=0
t= 55,en=1,a=3d,b=3d,c=3d,sum=3d,carry=3d,f_sum=b7,f_carry=0
t= 56,en=0,a=3e,b=3e,c=3e,sum=3e,carry=3e,f_sum=ba,f_carry=0
t= 57,en=1,a=3f,b=3f,c=3f,sum=3f,carry=3f,f_sum=bd,f_carry=0
t= 58,en=0,a=40,b=40,c=40,sum=40,carry=40,f_sum=c0,f_carry=0
t= 59,en=1,a=41,b=42,c=41,sum=42,carry=41,f_sum=c4,f_carry=0
t= 60,en=0,a=43,b=43,c=43,sum=43,carry=43,f_sum=c9,f_carry=0
t= 61,en=1,a=44,b=44,c=44,sum=44,carry=44,f_sum=cc,f_carry=0
t= 62,en=0,a=45,b=45,c=45,sum=45,carry=45,f_sum=cf,f_carry=0
t= 63,en=1,a=46,b=46,c=46,sum=46,carry=46,f_sum=d2,f_carry=0
t= 64,en=0,a=47,b=47,c=47,sum=47,carry=47,f_sum=d5,f_carry=0
t= 65,en=1,a=48,b=48,c=48,sum=48,carry=48,f_sum=d8,f_carry=0
t= 66,en=0,a=49,b=49,c=49,sum=49,carry=49,f_sum=db,f_carry=0
t= 67,en=1,a=4a,b=4a,c=4a,sum=4a,carry=4a,f_sum=de,f_carry=0
t= 68,en=0,a=4b,b=4b,c=4b,sum=4b,carry=4b,f_sum=e1,f_carry=0
t= 69,en=1,a=4c,b=4c,c=4c,sum=4c,carry=4c,f_sum=e4,f_carry=0
t= 70,en=0,a=4d,b=4d,c=4d,sum=4d,carry=4d,f_sum=e7,f_carry=0
t= 71,en=1,a=4e,b=4e,c=4e,sum=4e,carry=4e,f_sum=ea,f_carry=0
t= 72,en=0,a=4f,b=4f,c=4f,sum=4f,carry=4f,f_sum=ed,f_carry=0
t= 73,en=1,a=50,b=50,c=50,sum=50,carry=50,f_sum=f0,f_carry=0
t= 74,en=0,a=51,b=51,c=51,sum=51,carry=51,f_sum=f3,f_carry=0
t= 75,en=1,a=52,b=52,c=52,sum=52,carry=52,f_sum=f6,f_carry=0
t= 76,en=0,a=53,b=53,c=53,sum=53,carry=53,f_sum=f9,f_carry=0
t= 77,en=1,a=54,b=54,c=54,sum=54,carry=54,f_sum=fc,f_carry=0
t= 78,en=0,a=55,b=55,c=55,sum=55,carry=55,f_sum=ff,f_carry=0
t= 79,en=1,a=56,b=56,c=56,sum=56,carry=56,f_sum=2,f_carry=1
t= 80,en=0,a=57,b=57,c=57,sum=57,carry=57,f_sum=5,f_carry=1
t= 81,en=1,a=58,b=58,c=58,sum=58,carry=58,f_sum=8,f_carry=1
t= 82,en=0,a=59,b=59,c=59,sum=59,carry=59,f_sum=b,f_carry=1
t= 83,en=1,a=5a,b=5a,c=5a,sum=5a,carry=5a,f_sum=e,f_carry=1
t= 84,en=0,a=5b,b=5b,c=5b,sum=5b,carry=5b,f_sum=11,f_carry=1
t= 85,en=1,a=5c,b=5c,c=5c,sum=5c,carry=5c,f_sum=14,f_carry=1
t= 86,en=0,a=5d,b=5d,c=5d,sum=5d,carry=5d,f_sum=17,f_carry=1
t= 87,en=1,a=5e,b=5e,c=5e,sum=5e,carry=5e,f_sum=1a,f_carry=1
t= 88,en=0,a=5f,b=5f,c=5f,sum=5f,carry=5f,f_sum=1d,f_carry=1
t= 89,en=1,a=6f,b=6f,c=6f,sum=6f,carry=6f,f_sum=4d,f_carry=1
t= 90,en=0,a=7f,b=7f,c=7f,sum=7f,carry=7f,f_sum=7d,f_carry=1
t= 91,en=1,a=8f,b=8f,c=8f,sum=8f,carry=8f,f_sum=ad,f_carry=0
t= 92,en=0,a=9f,b=9f,c=9f,sum=9f,carry=9f,f_sum=dd,f_carry=0
t= 93,en=1,a=af,b=af,c=af,sum=af,carry=af,f_sum=d,f_carry=1
t= 94,en=0,a=bf,b=bf,c=bf,sum=bf,carry=bf,f_sum=3d,f_carry=1
t= 95,en=1,a=cf,b=cf,c=cf,sum=cf,carry=cf,f_sum=6d,f_carry=1
t= 96,en=0,a=df,b=df,c=df,sum=df,carry=df,f_sum=9d,f_carry=1
t= 97,en=1,a=ef,b=ef,c=ef,sum=ef,carry=ef,f_sum=cd,f_carry=1
t= 98,en=0,a=ff,b=ff,c=ff,sum=ff,carry=ff,f_sum=fd,f_carry=1
Stopped at time : 99 ns
APPLICATION OF CSA
Carry save
adder has efficient concept for implementation of high speed in many circuits. Carry
save adder applied in the partial product line of an array multiplier circuits
used to speed up the summation of the partial products in order to speed up the
carry propagation along the array. One of the main times saving techniques used
in the fastest design is the use of carry save adders to combine the partial
products into final answers.
Carry save represented
in joint module selection and retiming optimization as well as optimizes
technique. The use of carry save signal representation is a powerful technique
in high speed implementation of arithmetic circuits that solve the joint module
selection and retiming problem.
A carry save
adder is very fast where there is no carry propagation within each CSA cell. It
is only the final recombination of final carry and sum requires propagating
addition. T hat simply outputs the carry bit instead to propagating them to
side. Since it save all the carries from all the adds to the last stage and do
one carry look ahead addition or ripple carry addition at the last. Thus using
carry save adders avoids carry propagation and result in higher throughout. The
CSA design automatically avoids the delay in carryout bits. It is well known
that carry save arithmetic is a useful technique in the implementation of high
speed arithmetic functions. Carry save adder used widely in design because
carry save addition saves logic and time.
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