VLSI PROJECT: TRAFFIC LIGHT CONTROLLER

Program:::

No need to give test bench:

module naidu_traf(r1,r2,r3,r4,a1,a2,a3,a4,g1,g2,g3,g4);

output reg r1,r2,r3,r4,a1,a2,a3,a4,g1,g2,g3,g4;

reg clk;

parameter on=1'b1;

parameter off=1'b0;

parameter na_delay=5;

parameter am_delay=2;

initial r1=off;

initial r2=off;

initial r3=off;

initial r4=off;

initial g1=off;

initial g2=off;

initial g3=off;

initial g4=off;

initial a1=off;

initial a2=off;

initial a3=off;

initial a4=off;

always begin

#10clk=on;

#10clk=off;

end

always @(posedge clk)

begin

r1=on;r2=on;r3=on;g4=on;

light(r1,r2,r3,g4,na_delay);

a1=on;a2=off;a3=off;a4=off;

#20light(a1,a2,a3,a4,am_delay);

r4=on;r2=on;r3=on;g1=on;

#20light(r4,r2,r3,g1,na_delay);

a1=off;a2=on;a3=off;a4=off;

#20light(a1,a2,a3,a4,am_delay);

r4=on;r1=on;r3=on;g2=on;

#20light(r4,r1,r3,g2,na_delay);

a1=off;a2=off;a3=on;a4=off;

#20light(a1,a2,a3,a4,am_delay);

r4=on;r1=on;r2=on;g3=on;

#20light(r4,r1,r2,g3,na_delay);

end

task light(output c1,output c2,output c3,output c4,input[31:0] delay);

begin

repeat (delay)@(posedge clk);

 c1=off;

c2=off;

c3=off;

c4=off;

end

endtask

endmodule