VLSI PRACTICAL
COUNTERS:
FLIP FLOPS AND LATCHES:
4-BIT PARALLEL ADDER:
COUNTERS:
Q. Program to implement up counter without reset.
module rajupcounter(clk,count);
input clk;
output [3:0]count;
reg [3:0]count;
initial begin
count=0;
end
always@(posedge clk)
if(~clk)
count<=0;
else
count<=count+1;
endmodule
TESTBENCH-
module rajupcountertb_v;
//
Inputs
reg
clk;
//
Outputs
wire
[3:0] count;
//
Instantiate the Unit Under Test (UUT)
rajupcounter
uut (
.clk(clk),
.count(count)
);
initial
begin
//
Initialize Inputs
clk
= 0;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
endmodule
OUTPUT-
Q. Program to implement up-counter with reset.
module rajupcounter(clk,count,reset);
input clk,reset;
output [3:0]count;
reg [3:0]count;
initial begin
count=0;
end
always@(posedge clk)
if(reset)
count<=0;
else
count<=count+1;
endmodule
TETBENCH-
module rajupcountertb_v;
//
Inputs
reg
clk;
reg
reset;
//
Outputs
wire
[3:0] count;
//
Instantiate the Unit Under Test (UUT)
rajupcounter
uut (
.clk(clk),
.count(count),
.reset(reset)
);
initial
begin
//
Initialize Inputs
clk
= 0;reset=1;
#2
reset=0;
#100
$stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
OUTPUT-
Q. Program to implement down counter without reset.
module rajdowncounter(clk,count);
input clk;
output [3:0]count;
reg [3:0]count;
initial begin
count=10;
end
always@(posedge clk)
if(~clk)
count<=10;
else
count<=count-1;
endmodule
TESTBENCH-
module rajdowncountertb_v;
//
Inputs
reg
clk;
//
Outputs
wire
[3:0] count;
//
Instantiate the Unit Under Test (UUT)
rajdowncounter
uut (
.clk(clk),
.count(count)
);
initial
begin
//
Initialize Inputs
clk
= 0;
end
initial begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
//
Wait 100 ns for global reset to finish
//
Add stimulus here
endmodule
Q. Program to implement down counter with reset
module rajdowncounter(clk,count,reset);
input clk,reset;
output [3:0]count;
reg [3:0]count;
initial begin
count=10;
end
always@(posedge clk)
if(reset)
count<=10;
else
count<=count-1;
endmodule
TESTBENCH-
rajdowncounter uut (
.clk(clk),
.count(count),
.reset(reset)
);
initial
begin
//
Initialize Inputs
clk
= 0;reset=1;
#2
reset=0;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
// Wait 100 ns for global reset to finish
// Add stimulus here
endmodule
Q. Program to implement up-down counter.
module updowncounter(out,up_down,clk,reset);
output [7:0] out;
input up_down, clk, reset;
reg [7:0] out;
always @(posedge clk)
begin
if (reset)
out=8'b0;
else if(up_down)
out=out+1;
else
out=out-1;
end
endmodule
TESTBENCH-
module updowncountertb;
//
Inputs
reg
up_down;
reg
clk;
reg
reset;
//
Outputs
wire
[7:0] out;
//
Instantiate the Unit Under Test (UUT)
updowncounter
uut (
.out(out),
.up_down(up_down),
.clk(clk),
.reset(reset)
);
initial
begin
clk=1;
forever #2 clk=~clk;
end
initial
begin
//
Initialize Inputs
reset
= 1;up_down=0;
#2
reset=1;up_down=1;
#2
reset=0;up_down=1;
#40
reset=0;up_down=0;
//
Wait 100 ns for global reset to finish
#40
$stop;
// Add stimulus
here
end
endmodule
Q.Prgram to implement SR FlipFlop.
module sr_ff(q,qbar,clk,reset,s,r);
output q,qbar;
input clk,reset,s,r;
reg q;
always@(posedge clk)
begin
if(reset)
q<=0;
else if(s==0&&r==0)
q<=q;
else if(s==0&&r==1)
q<=0;
else if(s==1&&r==0)
q<=1;
else if(s==1&&r==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module sr_fftb;
//
Inputs
reg
clk;
reg
reset;
reg s;
reg r;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
sr_ff
uut (
.q(q),
.qbar(qbar),
.clk(clk),
.reset(reset),
.s(s),
.r(r)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
s
= 0;
r
= 0;
#10
reset=0;s=0;r=0;
#10
s=0;r=1;
#10
s=1;r=0;
#10
s=1;r=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
end
endmodule
OUTPUT-
Q. Prgram to implement JK FlipFlop.
module jk_flipflop(q,qbar,reset,clk,j,k);
output q,qbar;
input reset,clk,j,k;
reg q;
wire qbar;
always@(posedge clk)
begin
if(reset)
q<=0;
else if(j==0&&k==0)
q<=q;
else if(j==0&&k==1)
q<=0;
else if(j==1&&k==0)
q<=1;
else if(j==1&&k==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module jk_flipfloptb;
//
Inputs
reg
reset;
reg clk;
reg j;
reg k;
//
Outputs
wire q; wire qbar;
//
Instantiate the Unit Under Test (UUT)
jk_flipflop
uut (
.q(q),
.qbar(qbar),
.reset(reset),
.clk(clk),
.j(j),
.k(k)
);
initial
begin
//
Initialize Inputs
reset
= 1;
clk
= 0;
j
= 0;
k
= 0;
#10
reset=0;j=0;k=0;
#10
j=0;k=1;
#10
j=1;k=0;
#10
j=1;k=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
End
Endmodule
OUTPUT-
Q. Prgram to implement T FlipFlop.
module t_ff(q,clk,reset,t);
output q;
input clk,reset,t;
reg q;
always@(posedge clk)
if(reset)
begin
q<=0;
end
else if(t==0)
begin
q<=q;
end
else if(t==1)
begin
q<=~q;
end
endmodule
TESTBENCH-
module t_fftb;
//
Inputs
reg
clk;
reg
reset;
reg t;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
t_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.t(t)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
t
= 0;
#10 reset=0;t=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
#100;
// Add stimulus
here
end
endmodule
OUTPUT-
Q.Program to implement
D FlipFlop.
module d_ff(q,clk,reset,d);
output q;
input clk,reset,d;
reg q;
always @(posedge clk)
if(reset)
begin
q<=0;
end
else begin
q<=d;
end
endmodule
TESTBENCH-
module d_fftb;
//
Inputs
reg
clk;
reg
reset;
reg d;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
d_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.d(d)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 0;
d=0;
#10 reset=0;d=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
// Add stimulus here
End
Endmodule
OUTPUT-
Q. Program to implement SR Latch.
module sr_latch(q,qbar,clk,reset,s,r);
output q,qbar;
input clk,reset,s,r;
reg q;
always@(clk)
begin
if(reset)
q<=0;
else if(s==0&&r==0)
q<=1;
else if(s==0&&r==1)
q<=0;
else if(s==1&&r==0)
q<=1;
else if(s==1&&r==1)
q<=0;
end
assign qbar=~q;
endmodule
TESTBENCH-
module sr_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg s;
reg r;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
sr_ff
uut (
.q(q),
.qbar(qbar),
.clk(clk),
.reset(reset),
.s(s),
.r(r)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
s
= 0;
r
= 0;
#10
reset=0;s=0;r=0;
#10
s=0;r=1;
#10
s=1;r=0;
#10
s=1;r=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
// Add
stimulus here
end
endmodule
OUTPUT-
Q. Program to implement
JK Latch.
module jk_latch(q,qbar,reset,clk,j,k);
output q,qbar;
input reset,clk,j,k;
reg q;
wire qbar;
always@(clk)
begin
if(reset)
q<=0;
else if(j==0&&k==0)
q<=q;
else if(j==0&&k==1)
q<=0;
else if(j==1&&k==0)
q<=1;
else if(j==1&&k==1)
q<=1'bx;
end
assign qbar=~q;
endmodule
TESTBENCH-
module jk_latchtb;
//
Inputs
reg
reset;
reg
clk;
reg j;
reg k;
//
Outputs
wire q;
wire
qbar;
//
Instantiate the Unit Under Test (UUT)
jk_flipflop
uut (
.q(q),
.qbar(qbar),
.reset(reset),
.clk(clk),
.j(j),
.k(k)
);
initial
begin
//
Initialize Inputs
reset
= 1;
clk
= 0;
j
= 0;
k
= 0;
#10
reset=0;j=0;k=0;
#10
j=0;k=1;
#10
j=1;k=0;
#10
j=1;k=1;
#50
$stop;
end
initial begin
forever
#5 clk=~clk;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
endmodule
OUTPUT-
Q.Program to implement T Latch.
module t_latch(q,clk,reset,t);
output q;
input clk,reset,t;
reg q;
always@(clk)
if(reset)
begin
q<=0;
end
else if(t==0)
begin
q<=q;
end
else if(t==1)
begin
q<=~q;
end
endmodule
TESTBENCH-
module t_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg t;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
t_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.t(t)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 1;
t
= 0;
#10 reset=0;t=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
#100;
// Add
stimulus here
end
endmodule
OUTPUT-
Q.Program to implement D Latch.
module d_latch(q,clk,reset,d);
output q;
input clk,reset,d;
reg q;
always @(clk)
if(reset)
begin
q<=0;
end
else begin
q<=d;
end
endmodule
TESTBENCH-
module d_latchtb;
//
Inputs
reg
clk;
reg
reset;
reg d;
//
Outputs
wire q;
//
Instantiate the Unit Under Test (UUT)
d_ff
uut (
.q(q),
.clk(clk),
.reset(reset),
.d(d)
);
initial
begin
//
Initialize Inputs
clk
= 0;
reset
= 0;
d=0;
#10 reset=0;d=1;
#50 $stop;
end
initial
begin
forever
#5
clk=~clk;
//
Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
DECODERS AND ENCODERS:
AIM-To simulate decoder(3:8) and encoder(4:2) by giving inputs and outputs in vector form.
1) DECODER-
DATA FLOW-
module decc(a, y);
input [2:0] a;
output [7:0] y;
assign y[0]=(~a[0])&(~a[1])&(~a[2]);
assign y[1]=(~a[0])&(~a[1])&a[2];
assign y[2]=(~a[0])&(a[1])&(~a[2]);
assign y[3]=(~a[0])&a[1]&a[2];
assign y[4]=a[0]&(~a[1])&(~a[2]);
assign y[5]=a[0]&(~a[1])&a[2];
assign y[6]=a[0]&a[1]&(~a[2]);
assign y[7]=a[0]&a[1]&a[2];
endmodule
DAIGRAM-
TEST BENCH PROGRAMMING-
module decodd_v;
reg [2:0] a;
wire [7:0] y;
// Instantiate the Unit Under Test (UUT)
decc uut (
.a(a),
.y(y)
);
initial begin
// Initialize Inputs
a=3'b000;
#100 a=3'b001;
#100 a=3'b010;
#100 a=3'b011;
#100 a=3'b100;
#100 a=3'b101;
#100 a=3'b110;
#100 a=3'b111;
$stop;
end
endmodule
SIMULATION
2)-ENCODER-
DATA FLOW-
module enccc(a, y);
input [03:0] a;
output [01:0] y;
assign y[1]=a[3]|a[2];
assign y[0]=a[3]|a[1];
endmodule
DAIGRAM-
TEST BENCH PROGRAMMING-
module encccc_v;
reg [3:0] a;
wire [1:0] y;
// Instantiate the Unit Under Test (UUT)
enccc uut (
.a(a),
.y(y)
);
initial begin
// Initialize Inputs
a = 1000;
#100 a=0100;
#100 a=0010;
#100 a=0001
#100 $stop;
end
SIMULATION
OBSERVATION-By using xilinx we simulate the output of decoder and encoder.
CODE CONVERTERS:
Q. program to implement BCD to gray converter.
module rajbcd_gray(g,b);
output [3:0]g;
input [3:0]b;
reg [3:0]g;
always@(b)
begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule
Testbench-
module rajbcd_graytb;
//
Inputs
reg
[3:0] b;
//
Outputs
wire
[3:0] g;
//
Instantiate the Unit Under Test (UUT)
rajbcd_gray
uut (
.g(g),
.b(b)
);
initial begin
// Initialize Inputs
b
=0;
#5
b=1;
#5
b=2;
#5
b=3;
#5
b=4;
#5
b=5;
#5
b=6;
#5 b=7;
#5
b=8;
#5
b=9;
#5
b=10;
#5
b=11;
#5
b=12;
#5
b=13;
#5
b=14;
#5
b=15;
#50
$stop;
//
Wait 100 ns for global reset to finish
#100;
//
Add stimulus here
end
endmodule
Q. program to implement gray to BCD converter.
module rajgray2bcd(g,b);
output[3:0]b;
input [3:0]g;
reg [3:0]b;
always@(g)
begin
b[3]=g[3];
b[2]=b[3]^g[2];
b[1]=b[2]^g[1];
b[0]=b[1]^g[0];
end
endmodule
Testbench-
module rajgray2bcdtb;
//
Inputs
reg
[3:0] g;
//
Outputs
wire
[3:0] b;
//
Instantiate the Unit Under Test (UUT)
rajgray2bcd
uut (
.g(g),
.b(b)
);
initial begin
g=4'b0000;
#5 g=4'b0001;
#5 g=4'b0010;
#5 g=4'b0011;
#5 g=4'b0100;
#5 g=4'b0101;
#5 g=4'b0110;
#5 g=4'b0111;
#5 g=4'b1000;
#5 g=4'b1001;
#5 g=4'b1010;
#5 g=4'b1011;
#5 g=4'b1100;
#5 g=4'b1101;
#5 g=4'b1110;
#5 g=4'b1111;
#50 $stop;
// Initialize IS
//
Wait 100 ns for global reset to finish
#100;
// get the
forever loop inside
//
Add stimulus here
end
endmodule
Q. program to implement binary to gray converter.
module rajb2g(b,g);
input [3:0]b;
output [3:0]g;
reg [3:0]g;
always@(b)
begin
if(b==4'b0000)
g=4'b0000;
else if(b==4'b0001)
g=4'b0001;
else if(b==4'b0010)
g=4'b0011;
else if(b==4'b0011)
g=4'b0010;
else if(b==4'b0100)
g=4'b0110;
else if(b==4'b0101)
g=4'b0111;
else if(b==4'b0110)
g=4'b0101;
else if(b==4'b0111)
g=4'b0100;
else if(b==4'b1000)
g=4'b1100;
else if(b==4'b1001)
g=4'b1101;
else if(b==4'b1010)
g=4'b1111;
else if(b==4'b1011)
g=4'b1110;
else if(b==4'b1100)
g=4'b1010;
else if(b==4'b1101)
g=4'b1011;
else if(b==4'b1110)
g=4'b1001;
else if(b==4'b1111)
g=4'b1000;
end
endmodule
Testbench-
module rajb2gtb_v;
//
Inputs
reg
[3:0] b;
//
Outputs
wire
[3:0] g;
//
Instantiate the Unit Under Test (UUT)
rajb2g
uut (
.b(b),
.g(g)
);
initial
begin
//
Initialize Inputs
b=4’b0000;
#5
b=4’b0001;
#5
b=4’b0010;
#5
b=4’b0011;
#5
b=4’b0100;
#5
b=4’b0101;
#5
b=4’b0110;
#5
b=4’b0111;
#5
b=4’b1000;
#5
b=4’b1001;
#5
b=4’b1010;
#5
b=4’b1011;
#5
b=4’b1100;
#5
b=4’b1101;
#5
b=4’b1110;
#5
b=4’b1111;
#50
$stop;
//
Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
Output-
Q. program to implement gray to binary converter.
module rajg2b(g,b);
input [3:0]g;
output [3:0]b;
reg [3:0]b;
always@(g)
begin
if(g==4'b0000)
b=4'b0000;
else if(g==4'b0001)
b=4'b0001;
else if(g==4'b0010)
b=4'b0011;
else if(g==4'b0011)
b=4'b0010;
else if(g==4'b0100)
b=4'b0111;
else if(g==4'b0101)
b=4'b0110;
else if(g==4'b0110)
b=4'b0100;
else if(g==4'b0111)
b=4'b0101;
else if(g==4'b1000)
b=4'b1111;
else if(g==4'b1001)
b=4'b1110;
else if(g==4'b1010)
b=4'b1100;
else if(g==4'b1011)
b=4'b1101;
else if(g==4'b1100)
b=4'b1000;
else if(g==4'b1101)
b=4'b1001;
else if(g==4'b1110)
b=4'b1011;
else if(g==4'b1111)
b=4'b1010;
end
endmodule
Testbench-
module rajg2btb_v;
//
Inputs
reg
[3:0] g;
//
Outputs
wire
[3:0] b;
//
Instantiate the Unit Under Test (UUT)
rajg2b
uut (
.g(g),
.b(b)
);
initial
begin
// Initialize Inputs
g=4'b0000;
#5 g=4'b0001;
#5 g=4'b0010;
#5 g=4'b0011;
#5 g=4'b0100;
#5 g=4'b0101;
#5 g=4'b0110;
#5 g=4'b0111;
#5 g=4'b1000;
#5 g=4'b1001;
#5 g=4'b1010;
#5 g=4'b1011;
#5 g=4'b1100;
#5 g=4'b1101;
#5 g=4'b1110;
#5 g=4'b1111;
#50
$stop;
//
Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
ARITHMETIC LOGIC UNIT:
Q.To implement 4bit alu using behavioural modelling?
CODE-module raj_alu(a,b,s,o);
input
[3:0]a,b;
input
[2:0]s;
output
[4:0]o;
reg [4:0]o;
always@(s or
a or b)
begin
if(s==3'b000)
o=a+b;
else if
(s==3'b001)
o=b-a;
else if
(s==3'b010)
o=a*b;
else
if(s==3'b011)
o=a&&b;
else
if(s==3'b100)
o=a>>b;
else
if(s==3'b101)
o=a<<b;
else
if(s==3'b110)
o=a&b;
else
if(s==3'b111)
o=a|b;
end
endmodule
TEST BENCH-module raj_alutb;
//
Inputs
reg
[3:0]a;
reg
[3:0]b;
reg
[2:0] s;
//
Outputs
wire[4:0]
o;
//
Instantiate the Unit Under Test (UUT)
raj_alu
uut (
.a(a),
.b(b),
.s(s),
.o(o)
);
initial
begin
//
Initialize Inputs
a=1100; b=0110; s=000;
#1
a=0100; b=0011; s=001;
#1
a=0101; b=0100; s=010;
#1
a=1011; b=1101; s=011;
#1
a=0101; b=0001; s=100;
#1
a=0101; b=0001; s=101;
#1
a=1011; b=1011; s=110;
#1
a=0111; b=0101; s=111;
#50 $stop;
//
Wait 100 ns for global reset to finish
#100;
//
Add stimulus here
end
endmodule
Aim: implementation of 4 bit
parallel adder using verilog HDL.
State Diagram/ ASM
Chart (if any):
Attach
Graph/Simulation Waveforms:
Program code:
module fadd_gate(a,b,c,sum,ca);
output sum,ca;
input a,b,c;
wire p,q,r,s;
xor (p,a,b);
xor (sum,p,c);
and (q,a,b);
and (r,a,c);
and (s,a,c);
or (ca,p,q,r,s);
endmodule
module fadd(s,carr,a,b );
output [3:0]s;
output carr;
input [3:0]a,b;
fa f1(s[0],p,a[0],b[0],0);
fa f2(s[1],q,a[1],b[1],p);
fa f3(s[2],r,a[2],b[2],q);
fa f4(s[3],carr,a[3],b[3],r);
endmodule
Testbench:
module faa_test;
// Inputs
reg [3:0]
a;
reg [3:0]
b;
// Outputs
wire [3:0]
s;
wire carr;
//
Instantiate the Unit Under Test (UUT)
fadd uut (
.s(s),
.carr(carr),
.a(a),
.b(b)
);
initial
begin
//
Initialize Inputs
a
= 0;
b
= 0;
#5
a=4'b
1101;
b=4'b
1001;
//
Wait 100 ns for global reset to finish
#100;
//
Add stimulus here
end
endmodule
Console window output:
Result and
Discussion:
*first I had implement the full adder program and then
implement the program for 4 bit parallel adder in the same project.
*then give its test bench and generate the output waveform.
MULTIPLEXER AND DEMULTIPLEXER:
Aim: Implementing program for 4:1 mux(gatelevel),2:1
mux(gatelevel),4:1 demux(dataflow).
State Diagram/ ASM
Chart (if any):
Attach
Graph/Simulation Waveforms:
Program code:
Q1: Program for 4:1
mux in gatelevel.
ANS:
module mux_gatelevel(d0,d1,d2,d3,s1,s0,y);
input d0,d1,d2,d3,s1,s0;
output y;
wire s1bar,s0bar,y0,y1,y2,y3;
not n1(s1bar,s1);
not n2(s0bar,s0);
and a1(y0,s1bar,s0bar,d0);
and a2(y1,s1bar,s0,d1);
and a3(y2,s1,s0bar,d2);
and a4(y3,s1,s0bar,d2);
or o1(y,y0,y1,y2,y3);
endmodule
Q2:Program for demux in dataflow.
ANS:
module
demux_dataflow(in,s0,s1,y0,y1,y2,y3);
input in,s0,s1;
output y0,y1,y2,y3;
assign y0=((~s0)&(~s1)&in);
assign y1=((~s0)&s1&in);
assign y2=(s0&(~s1)&in);
assign y3=(s0&s1&in);
endmodule
Q3:Program for 2:1 mux in gatelevel.
ANS:
module mux_gatelevel2(d0,d1,s0,y);
input d0,d1,s0;
output y;
wire s0bar,y0,y1;
not n1(s0bar,s0);
and a1(y0,s0bar,d0);
and a2(y1,s0,d1);
or o1(y,y0,y1);
endmodule
Testbench:
*for 4:1 mux in gatelevel:
initial begin
//
Initialize Inputs
d0
= 0;
d1
= 0;
d2
= 0;
d3
= 0;
s1
= 0;
s0
= 0;
#5
d0=1;d1=0;d2=0;d3=0;s1=0;s0=0;
#5
d0=0;d1=0;d2=0;d3=0;s1=0;s0=1;
#5
d0=0;d1=1;d2=0;d3=0;s1=0;s0=1;
#5
d0=0;d1=0;d2=0;d3=0;s1=1;s0=0;
#5
d0=0;d1=0;d2=1;d3=0;s1=1;s0=0;
#5
d0=0;d1=0;d2=0;d3=0;s1=1;s0=1;
#5
d0=0;d1=0;d2=0;d3=1;s1=1;s0=1;
//
Wait 100 ns for global reset to finish
#100;
*for demux 4:1 in
dataflow:
initial begin
//
Initialize Inputs
d0
= 0;
d1
= 0;
s0
= 0;
#5
d0=1;d1=0;s0=0;
#5
d0=0;d1=0;s0=1;
#5
d0=0;d1=1;s0=1;
//
Wait 100 ns for global reset to finish
#100;
*for 2:1 mux in
gatelevel:
initial begin
//
Initialize Inputs
in
= 0;
s0
= 0;
s1
= 0;
#5
in=1;s0=0;s1=0;
#5
in=0;s0=0;s1=1;
#5
in=1;s0=0;s1=1;
#5
in=0;s0=1;s1=0;
#5
in=1;s0=1;s1=0;
#5
in=0;s0=1;s1=1;
#5
in=1;s0=1;s1=1;
//
Wait 100 ns for global reset to finish
#100;
Console window output:
*for 4:1 mux in gatelevel:
*for demux using dataflow method:
*for mux 2:1 using gatelevel:
Result and
Discussion:
*for
4:1 multiplexer using gatelevel: I found the output by choosing different
select lines s0 and s1 and assign them the different values like 00,01,10,11 to
their select lines and it has enable it first and so on inputs sequentially.i
had also first assign the value 0 and then 1 to its inputs to check whether its
circuit working correctly or not.
*for
4:1 demultiplexer in dataflow: I had
assign the values to s0 and s1 and do the rest as above described(i.e. in
dataflow method)
*for
2:1 multiplexer using gatelevel:here I had take two inputs d0 and d1,one select
line and one output.I assign the values in text fixture module to the select
line i.e 0 and 1 and change the values of input by assigning them values first
0 and then 1.
Learning Outcomes
(what I have learnt):
I have learnt to use the Xilinx ( ISE project navigator
M5.3d) and its various tools.I had used it for multiplexer and demultiplexer in
gatelevel and data flow method.I had understood the working of mux and demux
and its various applications.
*Multiplexer(data selector) is a device that allows digital
information from several sources to be routed on to a single line for
transmission over that line to a common destination.
*Demultiplexer is the reverse of above.
*here in these program I had understood the use of select
lines that are acting as data selectors
*I had understood the use of wires that are acting as internal
connection between input line and
output.
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