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Computer Arithmetic

and

Verilog HDL Fundamentals

Chapter 9

Decimal Subtraction

Verilog Code Figures

Page 470, Figure 9.5

//dataflow/structural mixed-design module for 9s complementer

module nines_compl (m, b, f);

input m;

input [3:0] b;

output [3:0] f;

//define internal nets

wire net2, net3, net4, net6, net7;

//instantiate the logic gates for the 9s complementer

xor2_df inst1 (

      .x1(b[0]),

      .x2(m),

      .z1(f[0])

      );

assign f[1] = b[1];

and2_df inst2 (

      .x1(~m),

      .x2(b[2]),

      .z1(net2)

      );

xor2_df inst3 (

      .x1(b[2]),

      .x2(b[1]),

      .z1(net3)

      );

and2_df inst4 (

      .x1(net3),

      .x2(m),

      .z1(net4)

      );

or2_df inst5 (

      .x1(net2),

      .x2(net4),

      .z1(f[2])

      );

and2_df inst6 (

      .x1(~m),

      .x2(b[3]),

      .z1(net6)

      );

and4_df inst7 (

      .x1(m),

      .x2(~b[3]),

      .x3(~b[2]),

      .x4(~b[1]),

      .z1(net7)

      );

or2_df inst8 (

      .x1(net6),

      .x2(net7),

      .z1(f[3])

      );

endmodule

//test bench for 9s complementer

module nines_compl_tb;

reg m;

reg [3:0] b;

wire [3:0] f;

initial                 //display variables

$monitor ("m=%b, b=%b, f=%b", m, b, f);

initial                 //apply input vectors

begin

//add -- do not complement

      #0       m = 1'b0;            b = 4'b0000;

      #10      m = 1'b0;            b = 4'b0001;

      #10      m = 1'b0;            b = 4'b0010;

      #10      m = 1'b0;            b = 4'b0011;                             

      #10      m = 1'b0;            b = 4'b0100;

      #10      m = 1'b0;            b = 4'b0101;

      #10      m = 1'b0;            b = 4'b0110;

      #10      m = 1'b0;            b = 4'b0111;

      #10      m = 1'b0;            b = 4'b1000;

      #10      m = 1'b0;            b = 4'b1001;

//subtract -- complement

      #10      m = 1'b1;            b = 4'b0000;

      #10      m = 1'b1;            b = 4'b0001;

      #10      m = 1'b1;            b = 4'b0010;

      #10      m = 1'b1;            b = 4'b0011;

      #10      m = 1'b1;            b = 4'b0100;

      #10      m = 1'b1;            b = 4'b0101;

      #10      m = 1'b1;            b = 4'b0110;

      #10      m = 1'b1;            b = 4'b0111;

      #10      m = 1'b1;            b = 4'b1000;

      #10      m = 1'b1;            b = 4'b1001;

      #10      $stop;

end

nines_compl inst1 (     //instantiate the module into the test bench

      .m(m),

      .b(b),

      .f(f)

      );

endmodule

Page 476, Figure 9.10

//structural bcd adder/subtractor

module add_sub_bcd2 (a, b, m, bcd, cout);

input [7:0] a, b;

input m;

output [7:0] bcd;

output cout;

//define internal nets

wire [7:0] f;

wire [7:0] sum;

wire cout3, aux_cy, cout7;

wire net3, net4, net9, net10;

//instantiate the logic for the low-order (units) stage [3:0]

//instantiate the 9s complementer

nines_compl inst1 (

      .m(m),

      .b(b[3:0]),

      .f(f[3:0])

      );

//instantiate the adder for intermediate sum for units stage

adder4 inst2 (

      .a(a[3:0]),

      .b(f[3:0]),

      .cin(m),

      .sum(sum[3:0]),

      .cout(cout3)

      );

//instantiate the logic gates

and2_df inst3 (

      .x1(sum[3]),

      .x2(sum[1]),

      .z1(net3)

      );

and2_df inst4 (

      .x1(sum[2]),

      .x2(sum[3]),

      .z1(net4)

      );

//continued on next page

or3_df inst5 (

   .x1(cout3),

   .x2(net3),

   .x3(net4),

   .z1(aux_cy)

   );

//instantiate the adder for the bcd sum [3:0]

adder4 inst6 (

      .a(sum[3:0]),

      .b({1'b0, aux_cy, aux_cy, 1'b0}),

      .cin(1'b0),

      .sum(bcd[3:0])

      );

//instantiate the logic for the high-order (tens) stage [7:4]

//instantiate the 9s complementer

nines_compl inst7 (

      .m(m),

      .b(b[7:4]),

      .f(f[7:4])

      );

//instantiate the adder for intermediate sum for tens stage

adder4 inst8 (

      .a(a[7:4]),

      .b(f[7:4]),

      .cin(aux_cy),

      .sum(sum[7:4]),

      .cout(cout7)

      );

//instantiate the logic gates

and2_df inst9 (

      .x1(sum[7]),

      .x2(sum[5]),

      .z1(net9)

      );

and2_df inst10 (

      .x1(sum[6]),

      .x2(sum[7]),

      .z1(net10)

      );

or3_df inst11 (

      .x1(cout7),

      .x2(net9),

      .x3(net10),

      .z1(cout)

      );

//instantiate the adder for the bcd sum [7:4]

adder4 inst12 (

      .a(sum[7:4]),

      .b({1'b0, cout, cout, 1'b0}),

      .cin(1'b0),

      .sum(bcd[7:4])

      );

endmodule

//test bench for the bcd adder subtractor

module add_sub_bcd2_tb;

reg [7:0] a, b;

reg m;

wire [7:0] bcd;

wire cout;

//display variables

initial

$monitor ("a=%b, b=%b, m=%b, bcd_hund=%b, bcd_tens=%b,

               bcd_units=%b",

            a, b, m, {{3{1'b0}}, cout}, bcd[7:4], bcd[3:0]);

//apply input vectors

initial

begin

//add bcd

      #0    a = 8'b1001_1001;    b = 8'b0110_0110;    m = 1'b0;

      #10   a = 8'b0010_0110;    b = 8'b0101_1001;    m = 1'b0;

      #10   a = 8'b0001_0001;    b = 8'b0011_0011;    m = 1'b0;

     #10   a = 8'b0000_1000;    b = 8'b0000_0101;    m = 1'b0;

      #10   a = 8'b0110_1000;    b = 8'b0011_0101;    m = 1'b0;

      #10   a = 8'b1000_1001;    b = 8'b0101_1001;    m = 1'b0;

      #10   a = 8'b1001_0110;    b = 8'b1001_0011;    m = 1'b0;

      #10   a = 8'b1001_1001;    b = 8'b0000_0001;    m = 1'b0;

      #10   a = 8'b0111_0111;    b = 8'b0111_0111;    m = 1'b0;

//subtract bcd

      #10   a = 8'b1001_1001;    b = 8'b0110_0110;    m = 1'b1;

      #10   a = 8'b1001_1001;    b = 8'b0110_0110;    m = 1'b1;

      #10   a = 8'b0011_0011;    b = 8'b0110_0110;    m = 1'b1;

      #10   a = 8'b0111_0110;    b = 8'b0100_0010;    m = 1'b1;

      #10   a = 8'b0111_0110;    b = 8'b1000_0111;    m = 1'b1;

      #10   a = 8'b0001_0001;    b = 8'b1001_1001;    m = 1'b1;

      #10   a = 8'b0001_1000;    b = 8'b0010_0110;    m = 1'b1;

      #10   a = 8'b0001_1000;    b = 8'b0010_1000;    m = 1'b1;

      #10   a = 8'b1001_0100;    b = 8'b0111_1000;    m = 1'b1;

      #10   $stop;

end

add_sub_bcd2 inst1 (    //instantiate the module into the test bench

      .a(a),

      .b(b),

      .m(m),

      .bcd(bcd),

      .cout(cout)

      );

endmodule

Page 484, Figure 9.15

//structural bcd adder subtractor

module add_sub_bcd3 (a, b, m_a_minus_b, m_b_minus_a,

                        bcd, cout);

input [7:0] a, b;

input m_a_minus_b, m_b_minus_a;

output [7:0] bcd;

output cout;

//define internal nets

wire [7:0] fa, fb;

wire [7:0] sum;

wire cout4, aux_cy, cout11;

wire net1, net5, net6, net12, net13;

//instantiate the logic for the low-order (units) stage [3:0]

or2_df inst1 (

      .x1(m_a_minus_b),

      .x2(m_b_minus_a),

      .z1(net1)

      );

//instantiate the 9s complementers

nines_compl inst2 (

      .m(m_b_minus_a),

      .b(a[3:0]),

      .f(fa[3:0])

      );

nines_compl inst3 (

      .m(m_a_minus_b),

      .b(b[3:0]),

      .f(fb[3:0])

      );

//instantiate the adder for the intermediate sum

//for units stage

adder4 inst4 (

      .a(fa[3:0]),

      .b(fb[3:0]),

      .cin(net1),

      .sum(sum[3:0]),

      .cout(cout4)

      );

//instantiate the logic gates

and2_df inst5 (

      .x1(sum[3]),

      .x2(sum[1]),

      .z1(net5)

      );

and2_df inst6 (

      .x1(sum[3]),

      .x2(sum[2]),

      .z1(net6)

      );

or3_df inst7 (

      .x1(cout4),

      .x2(net5),

      .x3(net6),

      .z1(aux_cy)

      );

//instantiate the adder for the bcd sum [3:0]

adder4 inst8 (

      .a(sum[3:0]),

      .b({1'b0, aux_cy, aux_cy, 1'b0}),

      .cin(1'b0),

      .sum(bcd[3:0])

      );

//instantiate the logic for the high-order (tens) stage [7:4]

//instantiate the 9s complementers

nines_compl inst9 (

      .m(m_b_minus_a),

      .b(a[7:4]),

      .f(fa[7:4])

      );

//continued on next page

nines_compl inst10 (

   .m(m_a_minus_b),

   .b(b[7:4]),

   .f(fb[7:4])

   );

//instantiate the adder for the intermediate sum

//for tens stage

adder4 inst11 (

      .a(fa[7:4]),

      .b(fb[7:4]),

      .cin(aux_cy),

      .sum(sum[7:4]),

      .cout(cout11)

      );

//instantiate the logic gates

and2_df inst12 (

      .x1(sum[7]),

      .x2(sum[5]),

      .z1(net12)

      );

and2_df inst13 (

      .x1(sum[7]),

      .x2(sum[6]),

      .z1(net13)

      );

or3_df inst14 (

      .x1(cout11),

      .x2(net12),

      .x3(net13),

      .z1(cout)

      );

//instantiate the adder for the bcd sum [7:4]

adder4 inst15 (

      .a(sum[7:4]),

      .b({1'b0, cout, cout, 1'b0}),

      .cin(1'b0),

      .sum(bcd[7:4])

      );

endmodule

//test bench for the bcd adder subtractor

module add_sub_bcd3_tb;

reg [7:0] a, b;

reg m_a_minus_b, m_b_minus_a;

wire [7:0] bcd;

wire cout;

//display variables

initial

$monitor ("a=%b, b=%b, m_a_minus_b=%b, m_b_minus_a=%b,

               bcd_hund=%b, bcd_tens=%b, bcd_units=%b",

            a, b, m_a_minus_b, m_b_minus_a,

               {{3{1'b0}}, cout}, bcd[7:4], bcd[3:0]);

//apply input vectors

initial

begin

//add bcd

      #0    m_a_minus_b = 1'b0;        m_b_minus_a = 1'b0;

            a = 8'b1001_1001;          b = 8'b0110_0110;

      #10   a = 8'b0010_0110;          b = 8'b0101_1001;

      #10   a = 8'b0001_0001;          b = 8'b0011_0011;

      #10   a = 8'b0000_1000;          b = 8'b0000_0101;

      #10   a = 8'b0110_1000;          b = 8'b0011_0101;

      #10   a = 8'b1000_1001;          b = 8'b0101_1001;

      #10   a = 8'b1001_0110;          b = 8'b1001_0011;

      #10   a = 8'b1001_1001;          b = 8'b0000_0001;

      #10   a = 8'b0111_0111;          b = 8'b0111_0111;

//subtract bcd a-b

      #10   m_a_minus_b = 1'b1;        m_b_minus_a = 1'b0;

            a = 8'b1001_1001;          b = 8'b0110_0110;

      #10   a = 8'b0011_0011;          b = 8'b0110_0110;

      #10   a = 8'b0111_0110;          b = 8'b0100_0010;

      #10   a = 8'b0111_0110;          b = 8'b1000_0111;

      #10   a = 8'b0001_0001;          b = 8'b1001_1001;

      #10   a = 8'b0001_1000;          b = 8'b0010_0110;

      #10   a = 8'b0001_1000;          b = 8'b0010_1000;

      #10   a = 8'b1001_0100;          b = 8'b0111_1000;

//subtract bcd b-a

      #10   m_a_minus_b = 1'b0;        m_b_minus_a = 1'b1;

            a = 8'b1001_1001;          b = 8'b0110_0110;

      #10   a = 8'b1001_1001;          b = 8'b0110_0110;

      #10   a = 8'b0011_0011;          b = 8'b0110_0110;

      #10   a = 8'b0111_0110;          b = 8'b0100_0010;

      #10   a = 8'b0111_0110;          b = 8'b1000_0111;

      #10   a = 8'b0001_0001;          b = 8'b1001_1001;

      #10   a = 8'b0001_1000;          b = 8'b0010_0110;

      #10   a = 8'b0001_1000;          b = 8'b0010_1000;

      #10   a = 8'b1001_0100;          b = 8'b0111_1000;

      #10      $stop;

end

//instantiate the module into the test bench

add_sub_bcd3 inst1 (

      .a(a),

      .b(b),

      .m_a_minus_b(m_a_minus_b),

      .m_b_minus_a(m_b_minus_a),

      .bcd(bcd),

      .cout(cout)

      );

endmodule