verilog
Code for RAM & ROM
Verilog code for single-port RAM in
read-first mode.
module raminfr (clk, en, we, addr, di, do);
input
clk;
input
we;
input
en;
input
[4:0] addr;
input
[3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule
verilog code for a single-port RAM in write-first mode.
verilog code for single-port RAM in no-change mode.
Verilog code for a ROM with registered address.
module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
reg
[4:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end
always @(raddr)
begin
if (en)
case(raddr)
4’b0000: data = 4’b0010;
4’b0001: data = 4’b0010;
4’b0010: data = 4’b1110;
4’b0011: data = 4’b0010;
4’b0100: data = 4’b0100;
4’b0101: data = 4’b1010;
4’b0110: data = 4’b1100;
4’b0111: data = 4’b0000;
4’b1000: data = 4’b1010;
4’b1001: data = 4’b0010;
4’b1010: data = 4’b1110;
4’b1011: data = 4’b0010;
4’b1100: data = 4’b0100;
4’b1101: data = 4’b1010;
4’b1110: data = 4’b1100;
4’b1111: data = 4’b0000;
default: data = 4’bXXXX;
endcase
end
endmodule
MEMORY READ MODULE
module mem
(r_wb,addr,d_q);
input r_wb; input [7:0]
addr;
inout [7:0] d_q;
reg [7:0] data [0:255];
assign d_q = (r_wb) ?
data[addr] : 8'hz ;
always @(r_wb)
if
(!r_wb) data[addr] = d_q ;
always @(addr)
if
(!r_wb) data[addr] = d_q ;
endmodule
MEMORY READ and WRITE MODULE
module ram_sp_sr_sw (
clk
, // Clock Input
address
, // Address Input
data
, // Data bi-directional
cs
, // Chip Select
we
, // Write Enable/Read Enable
oe
// Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input
Ports-----------------------
input clk ;
input [ADDR_WIDTH-1:0] address ;
input cs ;
input we ;
input oe ;
//--------------Inout
Ports-----------------------
inout [DATA_WIDTH-1:0] data
;
//--------------Internal
variables----------------
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg oe_r;
//--------------Code Starts
Here------------------
// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && !we)
? data_out : 8'bz;
// Memory Write Block
// Write Operation : When we = 1, cs = 1
always @ (posedge clk)
begin : MEM_WRITE
if ( cs
&& we ) begin
mem[address] = data;
end
end
// Memory Read Block
// Read Operation : When we = 0, oe = 1, cs = 1
always @ (posedge clk)
begin : MEM_READ
if (cs
&& !we && oe) begin
data_out = mem[address];
oe_r =
1;
end else
begin
oe_r =
0;
end
end
endmodule // End of Module ram_sp_sr_sw
Good,thank's.
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