VLSI PRACTICAL
AIM
: Verilog Code to detect the Sequence 0110
Program Code:-
module meelay(in, clk, reset, out);
input
in,clk,reset;
output
out;
reg out;
reg [3:0] p_st,nx_st;
parameter
s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;
initial
p_st=s0;
always@(posedge clk)
begin
case(p_st)
s0:begin
out=0;
if(in==1'b0)
nx_st=s1;
else
nx_st=s0;
end
s1:begin
out=0;
if(in==1'b1)
nx_st=s2;
else
nx_st=s1;
end
s2:begin
out=0;
if(in==1'b1)
nx_st=s3;
else
nx_st=s1;
end
s3:begin
out=0;
if(in==1'b0)
nx_st=s4;
else
nx_st=s0;
end
s4:begin
out=1;
if(in==1'b0)
nx_st=s1;
else
nx_st=s2;
end
endcase
end
always@(posedge
clk)
begin
if(reset)
p_st=s0;
else
p_st=nx_st;
end
endmodule
Testbench:
module meelaytb;
//
Inputs
reg
in;
reg
clk;
reg
reset;
//
Outputs
wire
out;
//
Instantiate the Unit Under Test (UUT)
meelay uut (
.in(in),
.clk(clk),
.reset(reset),
.out(out)
);
initial
begin
in=0;
reset=1;
clk=1;
end
always
#5
clk=~clk;
initial
begin
//
Initialize Inputs
#10
in=0;reset=0;
#10
in=1;reset=0;
#10
in=1;reset=0;
#10
in=0;reset=0;
#10
in=1;reset=0;
#10
in=1;reset=0;
#10
in=0;reset=0;
#10
in=0;reset=0;
#10
in=1;reset=0;
#10 in=1;reset=0;
#10
in=0;reset=0;
#10
in=1;reset=0;
#10
in=1;reset=0;
#10
in=0;reset=0;
#10
in=1;reset=0;
#10
in=1;reset=0;
#10
in=0;reset=0;
#10
in=1;reset=0;
#10
in=1;reset=0;
#10
in=0;reset=0;
//
Wait 100 ns for global reset to finish
//
Add stimulus here
end
endmodule
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